Total dose radiation hardening and testing issues of GaAs static memories

Author

Srivastava, A. ; Ganeshan, M.

Author_Institution

Dept. of Electr. Eng., Louisiana State Univ., Baton Rouge, LA, USA

fYear

1994

fDate

8-9 Aug 1994

Firstpage

135

Lastpage

140

Abstract

A test chip in GaAs (E/D) technology has been designed and implemented in 1.2 μm MOSIS GaAs design rules. The unpackaged devices have been subjected to 1.5 keV Al-K_α X-rays and degradations in zero bias threshold voltage and device transconductance of n-channel E and D-MESFETs have been studied. A modified GaAs SRAM cell design, incorporating a circuits design to minimize degradations in noise margin due to degradations in device parameters at large radiation doses has been proposed

Keywords

III-V semiconductors; MESFET integrated circuits; SRAM chips; X-ray effects; field effect memory circuits; gallium arsenide; integrated circuit design; integrated circuit noise; integrated circuit testing; radiation hardening (electronics); 1.2 micron; 1.5 keV; GaAs; GaAs E/D technology; MOSIS design rules; SRAM cell design; X-rays; device transconductance; memory chip testing; n-channel MESFETs; noise margin; static memories; test chip; total dose radiation hardening; unpackaged devices; zero bias threshold voltage; Circuit noise; Circuit synthesis; Degradation; Gallium arsenide; Radiation hardening; Random access memory; Testing; Threshold voltage; Transconductance; X-rays;

fLanguage

English

Publisher

ieee

Conference_Titel

Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on

Conference_Location

San Jose, CA

Print_ISBN

0-8186-6245-X

Type

conf

DOI

10.1109/MTDT.1994.397184

Filename

397184