On VLSI statistical timing analysis and optimization

Performance variation has become an increasingly critical design objective as VLSI technology scales into the nanometer domain wherein parametric variations are inevitably significant. This paper presents an overview of statistical timing analysis in a new perspective, including clarification of problem formulation, an iterative refinement methodology, and iterative signal integrity effects aware statistical timing analysis methods. This paper also demonstrates that statistical physical design optimization does not produce noticeably different results than traditional physical design, and performance variation tolerance needs to be achieved by other techniques, e.g., asynchronous circuit design.