• DocumentCode
    2650396
  • Title

    Logical effort of higher valency adders

  • Author

    Harris, David

  • Author_Institution
    Harvey Mudd Coll., Claremont, CA, USA
  • Volume
    2
  • fYear
    2004
  • fDate
    7-10 Nov. 2004
  • Firstpage
    1358
  • Abstract
    Higher valency parallel prefix adders reduce the number of logic levels at the expense of greater fan-in at each level. This paper uses the method of logical effort to evaluate the tradeoffs of higher valency for static and dynamic implementations of various adder architectures.
  • Keywords
    adders; logic gates; valency; adder architectures; higher valency adders logical effort; logic levels reduction; parallel prefix adders; Adders; Circuits; Computer architecture; Delay estimation; Educational institutions; Libraries; Logic; Microprocessors; Propagation delay; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference on
  • Print_ISBN
    0-7803-8622-1
  • Type

    conf

  • DOI
    10.1109/ACSSC.2004.1399375
  • Filename
    1399375
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2650396