Temperature insensitive design for power gated circuits

With rapid scaling in Deep Sub-micron (DSM) technologies, the difference between supply and threshold voltage is decreasing rapidly. This makes delay of the circuit highly sensitive to gate overdrive voltage with temperature fluctuations. In sub-100nm technologies, the delay of the circuit decreases with increase in temperature, known as Inverted Temperature Dependence(ITD) at nominal supply voltage. This effect was reverse in the older technologies. Scaling supply voltage further increases delay variation with temperature changes causing severe timing imbalance in the circuit. Further for a Power Gated circuit where a high threshold sleep transistor is inserted, timing is a critical issue. Temperature insensitive FBB with and without voltage scaling is proposed in the paper to achieve circuit tolerance to delay variations and hence temperature fluctuations.