A low power self-sampling IF FSK receiver

A low power IF FSK receiver is presented. The receiver consists of one limiter and one self-sampling FSK demodulator. The limiter uses the replica biasing circuit technique to avoid the effects of PVT variation. To minimize the power consumption, a low supply VCDL is adopted, and the reference clock frequency of DLL is also decreased. The receiver has been implemented in 0.18 ¿m CMOS process and the simulated results show that the receiver could accurately demodulate the signal with a data rate of 2 Mbps and a IF carrier frequency of 10 MHz and achieves a IF carrier frequency offset tolerance of 1 MHz. The power consumption of the IF FSK receiver is 2.64 mW. The demodulator part consumes only 0.48 mW.