DocumentCode
2652514
Title
Scanning datapaths: a fast and effective partial scan selection technique
Author
Flottes, M.L. ; Pires, R. ; Rouzeyre, B. ; Volpe, L.
Author_Institution
Lab. d´´Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
fYear
1998
fDate
23-26 Feb 1998
Firstpage
921
Lastpage
922
Abstract
Partial scan DFT is a commonly used technique for improving testability of sequential circuits while maintaining overhead as low as possible. In this context, the selection of the partial scan chain is usually performed at gate-level. In this paper, we present a method for quickly selecting the partial Scan Chain (SC) in datapath-like circuits. The so-obtained SC is such that the number of scan FFs is optimized and such that the achievable fault coverage is the same than with full scan approach
Keywords
design for testability; flip-flops; logic testing; sequential circuits; datapaths scanning; fault coverage; partial scan DFT; partial scan chain; partial scan selection technique; sequential circuits; testability; Algorithm design and analysis; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit testing; Logic testing; Registers; Robots; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655969
Filename
655969
Link To Document