A cost efficient LDPC decoder for DVB-S2

Author

Ying, Yan ; Bo, Dan ; Huang, Shuangqu ; Xiang, Bo ; Chen, Yun ; Zeng, Xiaoyang

Author_Institution

Dept. of Microelectron., Fudan Univ., Shanghai, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

1007

Lastpage

1010

Abstract

Based on the min-sum algorithm, this paper proposes an LDPC decoder integrating the TDMP schedule, which could achieve low complexity as well as good performance. The LDPC decoder is for DVB-S2, which includes 11 kinds of code rates with a block size of 64800. Based on SMIC 0.13 Â¿m standard CMOS process, the LDPC decoder has an estimation area of 14 mm², a throughput of 135 Mbps with a frequency of 105 MHz and maximum iteration number of 30,which shows advantage over previous DVB-S2 LDPC decoders.

Keywords

CMOS integrated circuits; digital video broadcasting; message passing; parity check codes; turbo codes; DVB-S2; LDPC decoder; SMIC standard CMOS process; TDMP schedule; bit rate 135 Mbit/s; digital video broadcasting via satellite; frequency 105 MHz; maximum iteration number; min-sum algorithm; size 0.13 mum; turbo decoding message passing; Application specific integrated circuits; Costs; Digital video broadcasting; Forward error correction; Frequency estimation; Iterative decoding; Microelectronics; Parity check codes; Satellite broadcasting; Throughput; DVB-S2; LDPC coeds; TDMP schedule; min-sum;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351522

Filename

5351522