A Reliability-Aware LDPC Code Decoding Algorithm

With the continuing downscaling of microelectronic technology, chip reliability becomes a great threat to the design of future complex microelectronic systems. Hence increasing the robustness of chip implementations in terms of tolerating errors becomes mandatory. In this paper we present reliability-aware extensions of the LDPC decoding algorithm. We exploit application specific fault tolerance of the decoding algorithm combined with modifications on the algorithmic level to increase the reliability of a decoder implementation. These modifications lead to a LDPC decoder implementation which tolerates sporadic errors that occur in critical components. To the best of our knowledge this is the first investigation of the LDPC decoding algorithm in terms of implementation reliability.