Design and implementation of configurable extract instructions targeted at stream cipher processing

High-performance and flexible configurable extract instructions targeted at stream cipher processing are proposed by analyzing the structures and operating characteristics of more than forty public stream cipher algorithms in this paper. The extract instructions are designed to sustain four different data widths, and ten parallel extract modes are exploited by instruction level parallelism based on VLIW system structure. Further more, the corresponding reconfigurable hardware circuit is implemented. By configurating the hardware circuit, the extract of different data width and different parallel mode can be gained efficiently, so the circuit can be used as an important accelerated unit in special processing for stream cipher.