A fast-lock digital delay-locked loop controller

A fast-lock digital delay-locked loop (DLL) is presented in this paper. A delay compensation circuit (DCC ) is used to achieve short lock time. The DLL´s initial value is controlled by the DCC, so that initial delay time of the delay line can be located in the expected scope and there is only one stable state in various process, voltage, and temperature (PVT) conditions. Since the delay time of each delay cell changes based on the variations of PVT conditions, the output values generated by the DCC are determinate of the PVT conditions in the chip. Thus the DLL´s initial state changes according to the detected PVT conditions, and the initial large phase difference is eliminated by the DCC. So it can be fast locked and only has one stable state. The proposed digital DLL overcomes the drawbacks of traditional DLL which may have more than one stable state. The HSPICE simulation results show that the proposed digital DLL circuit achieves fine accuracy and the maximum lock time is 16 clock cycles.