Fast configuration architecture of FPGA suitable for bitstream compression

In this paper, fast configuration architecture of FPGA suitable for bitstream compression is proposed and implemented for FDP2009-II-SOPC (FDP2009-II-SOPC: Fudan Programmable device 2009-II-SOPC) FPGA with SMIC 0.13 CMOS process. This circuit features an addressable configuration register and the internal frame decoder that makes a 32-bit memory cell of FPGA addressable. The improved configuration circuit which can configuration every 32bit memory cells could provide faster configuration speed and more flexible partial configuration operations. The die size of FDP2009-II-SOPC is about 6.3 mm*4.5mm=28.35 mm² and the area of this configuration circuit is about 1.7 mm². The post layout simulation shows that this fast configuration circuit of FDP2009-II-SOPC FPGA could work correctly and efficiently and the configuration time is less than 53% of that of Xilinx VirtexII series FPGA.