VLSI implementation of high-speed SHA-256

Author

Bai, Ling ; Li, Shuguo

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2009

fDate

20-23 Oct. 2009

Firstpage

131

Lastpage

134

Abstract

To accelerate the speed of iterative computation for the existing SHA-256 algorithm, using 7-3-2 array compressor is proposed to reduce the critical path delay in this paper. The frequency of the proposed scheme is 1.7 times higher than other VLSI implementations under the same process. In addition, the paper designs a new universal architecture for implementing SHA-2 algorithms. The design is synthesized with the slow library of Synopsys Design Compiler in SMIC 0.18 Â¿m CMOS process. Its function has been verified sufficiently on FPGA. Furthermore, compared with the existing SHA-256 core, the results of the ASIC synthesis and FPGA verification are more preferable. This design is convenient to implant into SoC and embedded system with the versatile architecture and high clock frequency.

Keywords

CMOS logic circuits; VLSI; application specific integrated circuits; critical path analysis; field programmable gate arrays; iterative methods; 7-3-2 array compressor; ASIC synthesis; CMOS process; FPGA verification; SHA-256; VLSI; critical path delay; iterative computation; synopsys design compiler; Acceleration; Algorithm design and analysis; CMOS process; Computer architecture; Delay; Field programmable gate arrays; Frequency; Iterative algorithms; Libraries; Very large scale integration; 7-3-2 compressor; FPGA; SHA-256; critical path;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC, 2009. ASICON '09. IEEE 8th International Conference on

Conference_Location

Changsha, Hunan

Print_ISBN

978-1-4244-3868-6

Electronic_ISBN

978-1-4244-3870-9

Type

conf

DOI

10.1109/ASICON.2009.5351591

Filename

5351591