Repeater insertion combined with LGR methodology for on-chip interconnect timing optimization

A combination of repeater insertion with a novel LGR (logic gates as repeater) technique is presented, providing a methodology for delay optimization of CMOS logic circuits with RC interconnects. The traditional interconnect segmentation by insertion of repeaters is generalized to segmentation by distributing logic gates over interconnect lines and adding a reduced number of repeaters. Expressions for optimal segment length, optimal number of additional repeaters and scaling factors for both gates and repeaters are derived. An iterative solution is presented. Optimization results for several circuits are presented, showing significant improvement in performance in comparison with traditional repeater insertion.