DocumentCode
2656024
Title
Low-voltage and high-speed FPGA I/O cell design in 90nm CMOS
Author
Zhang, Nan ; Wang, Xin ; Tang, He ; Wang, Albert ; Wang, ZhiHua ; Chi, Baoyong
Author_Institution
Tsinghua Univ., Beijing, China
fYear
2009
fDate
20-23 Oct. 2009
Firstpage
533
Lastpage
536
Abstract
This paper reports design and fabrication of a low-voltage high-speed field programmable gate array (FPGA) I/O cell (IOC) IC in a commercial 90 nm CMOS technology. This IOC IC supports forty common industrial I/O standards. This design features function-based I/O standard partitioning for simpler architecture, block sharing for smaller size and lower power dissipation, multiple-supply design trade-off, programmable drive capability and signal integrity recovery, etc. Measurement agrees well with simulation.
Keywords
CMOS integrated circuits; field programmable gate arrays; logic design; CMOS; field programmable gate array; high-speed FPGA I/O cell design; size 90 nm; CMOS technology; Design methodology; Field programmable gate arrays; Helium; High speed integrated circuits; Power dissipation; Radio frequency; Signal design; Transceivers; Voltage; FPGA; I/O cell; high speed; low voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 2009. ASICON '09. IEEE 8th International Conference on
Conference_Location
Changsha, Hunan
Print_ISBN
978-1-4244-3868-6
Electronic_ISBN
978-1-4244-3870-9
Type
conf
DOI
10.1109/ASICON.2009.5351636
Filename
5351636
Link To Document