Design and implementation of area-efficient DVB-S2 BCH decoder

BCH code is adopted as a part of the Forward Error Correction subsystem of DVB-S2 system, which is the next generation digital video broadcast system based on satellite wireless communication system. As DVB-S2 system uses very long code length and multiple code modes, full compatible BCH decoder is high area cost. In order to reduce the area cost of the full compatible DVB-S2 BCH decoder, we have modified the VLSI implementation of Berlekamp Massey Algorithm for key equation solver which is the main part of BCH decoder, rebuilt the Galois Filed Multiplications including the constant Galois Field Multiplications and the general Galois Field Multiplications. In order to support all the code modes and Adaptive Coded Modulation, a novel duo-pipeline reconfigurable architecture have been proposed, which can support code mode switching without stalling the symbol stream. We have implemented the decoder with verilog HDL, and have evaluated it by FPGA platform and ASIC library. The results show that the logic area of the decoder is at least 13% fewer than other existing decoders.