Optimum design of spacer-type storage nodes in recessed channel structure for 2-bit/cell SONOS flash memory cell

Author

Han, Kyoung-Rok ; Jung, H. ; Park, K.H. ; Kim, Y.M. ; Choi, B.-K. ; Jung, S.-G. ; Lee, Jong-Ho

Author_Institution

Kyungpook Nat. Univ., Taegu

fYear

2007

fDate

12-14 Dec. 2007

Firstpage

1

Lastpage

2

Abstract

In this paper an optimum device design of SONOS flash memory devices with spacer-type charge trapping layer formed on the side surface of recessed channel region is discussed. The device can be applied to high- density and high-performance 50 nm NOR-type flash memory cell. The nitride length of 60 nm from the top of the body is reasonable 2-bit/cell operation at a S/D junction depth of 30 nm.

Keywords

CMOS logic circuits; CMOS memory circuits; flash memories; integrated circuit design; logic design; CMOS technology; NOR-type flash memory cell; S-D junction; SONOS flash memory cell; charge trapping layer; depth 30 nm; optimum device design; recessed channel region; recessed channel structure; size 50 nm; size 60 nm; spacer-type storage nodes; CMOS technology; Channel hot electron injection; Doping profiles; Educational institutions; Flash memory; Flash memory cells; Geometry; Nonvolatile memory; SONOS devices; Scalability;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Device Research Symposium, 2007 International

Conference_Location

College Park, MD

Print_ISBN

978-1-4244-1892-3

Electronic_ISBN

978-1-4244-1892-3

Type

conf

DOI

10.1109/ISDRS.2007.4422282

Filename

4422282