DocumentCode
2657246
Title
Power and timing modeling for ASIC designs
Author
Roethig, Wolfgang ; Zarkesh, Amir M. ; Andrews, Michael
Author_Institution
LSI Logic Corp., Milpitas, CA, USA
fYear
1998
fDate
23-26 Feb 1998
Firstpage
969
Lastpage
970
Abstract
This paper presents a unified power and timing modeling for ASIC libraries. This ASIC library is being standardized and targeted for a design flow, where timing analysis is complemented by power analysis. We show benchmark results from new industrial gate-level power analysis tools
Keywords
application specific integrated circuits; digital integrated circuits; integrated circuit design; integrated circuit modelling; logic CAD; timing; ASIC designs; benchmark results; design flow; digital ICs; industrial gate-level power analysis tools; logic CAD; power modeling; timing modeling; Analytical models; Application specific integrated circuits; Capacitance; Delay; Energy consumption; Frequency estimation; Libraries; Object oriented modeling; Semiconductor device modeling; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.655993
Filename
655993
Link To Document