DocumentCode
2657853
Title
CMOS combinational circuit sizing by stage-wise tapering
Author
Pullela, S. ; Panda, R. ; Dharchoudhury, A. ; Vijayan, G. ; Blaauw, D.
Author_Institution
High Frequency Design Methods & Technol., Motorola Inc., Austin, TX, USA
fYear
1998
fDate
23-26 Feb 1998
Firstpage
985
Lastpage
986
Abstract
We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain and uses tapering constants based on the position of a stage in a circuit, and the position of a transistor in a stack
Keywords
CMOS logic circuits; circuit CAD; circuit optimisation; combinational circuits; logic CAD; multivalued logic circuits; CMOS combinational circuit; buffer chain; combinational circuit sizing; linear time procedure; multi-input gates; restructuring optimization procedure; stage-wise tapering; tapering constants; total area; CMOS technology; Capacitance; Combinational circuits; DH-HEMTs; Delay; Design methodology; Frequency; Iterative methods; Linear programming; Optimization methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation and Test in Europe, 1998., Proceedings
Conference_Location
Paris
Print_ISBN
0-8186-8359-7
Type
conf
DOI
10.1109/DATE.1998.656001
Filename
656001
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