DocumentCode
2657888
Title
Design and Realization of FFT Implementation Unit Based on FPGA
Author
Yu, Song ; Xingye, Lin ; Shuang, Zhai
Author_Institution
Comput. Sci. & Eng, Inst. ChangChun Univ. of Technol., Changchun, China
fYear
2011
fDate
4-6 Nov. 2011
Firstpage
119
Lastpage
122
Abstract
This paper describes the arithmetic principle and discipline of FFT, analyzes rotation factor and data address of the node. It adopts flexible Verilog HDL to design and realize the data address unit of FFT implementation which is 64-point by radix-2. It uses Alter a company´s PLD software Quartus II 8.0 (32-Bit) to compile and form top-level entity.
Keywords
fast Fourier transforms; field programmable gate arrays; hardware description languages; programmable logic devices; FPGA; PLD software Quartus II 8.0; Verilog HDL; arithmetic principle; data address; fast Fourier transforms; field programmable gate arrays; radix-2; rotation factor; word length 32 bit; Algorithm design and analysis; Discrete Fourier transforms; Educational institutions; Field programmable gate arrays; Hardware; Hardware design languages; Signal processing algorithms; Butterfly-calculation; FFT; FPGA; Rotation Cfactor; Verilog HDL Introduction;
fLanguage
English
Publisher
ieee
Conference_Titel
Multimedia Information Networking and Security (MINES), 2011 Third International Conference on
Conference_Location
Shanghai
Print_ISBN
978-1-4577-1795-6
Type
conf
DOI
10.1109/MINES.2011.65
Filename
6103735
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