High-speed VLSI arithmetic processor architectures using hybrid number representation

The design of high-speed architectures is addressed for fixed-point, two´s-complement, bit-parallel, pipelined, multiplication, division and square-root operations. The architectures presented make use of hybrid number representations (i.e. the input and output numbers are presented using two´s complement representation, and the internal numbers are represented using radix-2 redundant representation). A fast, new conversion scheme for converting radix-2 redundant numbers to two´s-complement binary numbers is presented, and this is used to design a reduced latency bit-parallel multiplier. The novel sign-multiplexing scheme helps detect the sign of a redundant number very quickly and is used in combination with the remainder conditioning scheme to achieve very high speed in fixed-point division and square-root operators. These architectures require fewer pipelining latches than their conventional two´s-complement counterparts. Reduction in latency without sacrificing clock speed has resulted in reduced computation time for these operations