Tradeoffs in partitioning for waveform relaxation on multicomputers

Author

Peterson, Lena ; Mattisson, Sven

Author_Institution

Dept. of Appl. Electron., Lund Univ., Sweden

fYear

1990

fDate

1-3 May 1990

Firstpage

1581

Abstract

A study of static circuit partitioning algorithms for waveform relaxation (WR) on a multicomputer is presented. For such a computer there is an important tradeoff between the irregularity in partitioning and the achievable parallelism. Also, the importance of accuracy in certain steps in the partitioning calculation has been investigated. Topological methods are compared with several other methods which try to estimate the convergence factor for the WR iterations. For digital CMOS circuits it is found that only the close neighborhood to a circuit node (nearest neighbors) influences the value of the worst-case coupling. The conductive coupling is the essential part to consider in the partitioning. For a few circuits (mostly circuits with cross-coupling) the capacitive coupling must also be included in the partitioning. It is, however, hard to find an exact limit for the convergence factor estimate

Keywords

CMOS integrated circuits; circuit analysis computing; digital integrated circuits; iterative methods; parallel algorithms; waveform analysis; capacitive coupling; circuit node; conductive coupling; convergence factor; digital CMOS circuits; parallelism; partitioning; static circuit partitioning algorithms; waveform relaxation; worst-case coupling; CMOS digital integrated circuits; Circuit simulation; Circuit testing; Computational modeling; Convergence; Coupling circuits; Equations; Nearest neighbor searches; Parallel processing; Partitioning algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112437

Filename

112437