• DocumentCode
    2660810
  • Title

    A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators

  • Author

    Shu, Yun-Shiang

  • Author_Institution
    MediaTek Inc., Hsinchu, Taiwan
  • fYear
    2012
  • fDate
    13-15 June 2012
  • Firstpage
    26
  • Lastpage
    27
  • Abstract
    A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021mm2. Dynamic comparators with digitally controlled built-in offset are realized with imbalanced tails. Half of the comparators are substituted with simple SR latches. The ADC achieves SNDRs of 36.2dB and 33.1dB at DC and Nyquist, respectively, while consuming 11mW from a 1.1V supply.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; comparators (circuits); flip-flops; CMOS; SR latch; comparator; digitally controlled built-in offset; dynamic comparator; fully dynamic flash ADC; noise figure 36.2 dB to 33.1 dB; power 11 mW; size 40 nm; voltage 1.1 V; CMOS integrated circuits; Capacitors; Latches; Noise; Resistors; Strontium; Transistors; comparator offset calibration; dynamic ADC; flash ADC; interpolation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2012 Symposium on
  • Conference_Location
    Honolulu, HI
  • Print_ISBN
    978-1-4673-0848-9
  • Electronic_ISBN
    978-1-4673-0845-8
  • Type

    conf

  • DOI
    10.1109/VLSIC.2012.6243772
  • Filename
    6243772
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2660810