• DocumentCode
    2661660
  • Title

    An algorithm for the multi-level minimization of Reed-Muller representations

  • Author

    Saul, Jonathan

  • Author_Institution
    Dept. of Electr. & Electron. Eng., Bristol Univ., UK
  • fYear
    1991
  • fDate
    14-16 Oct 1991
  • Firstpage
    634
  • Lastpage
    637
  • Abstract
    There is interest currently in using Reed-Muller equations as a way of representing and manipulating switching functions, and as a means of designing circuits based on exclusive-OR gates. There are only two-level Reed-Muller minimizers in use, although the need for a multi-level minimizer has been identified. A procedure for multi-level Reed-Muller minimization has been developed. It introduces a Reed-Muller factored form and uses algebraic algorithms for factorization decomposition, resubstitution, collapsing, and extraction of common cubes and sub-expressions. The procedure has been implemented in C as a series of packages which have been added to MISII, and benchmark comparisons with minimal two-level representations are favorable
  • Keywords
    logic CAD; many-valued logics; minimisation of switching nets; switching functions; MISII; collapsing; decomposition; exclusive-OR gates; factorization; multi-level Reed-Muller minimization; resubstitution; switching functions; Arithmetic; Automatic testing; Circuit synthesis; Circuit testing; Digital circuits; Equations; Error correction; Minimization methods; Packaging; Programmable logic arrays;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design: VLSI in Computers and Processors, 1991. ICCD '91. Proceedings, 1991 IEEE International Conference on
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    0-8186-2270-9
  • Type

    conf

  • DOI
    10.1109/ICCD.1991.139990
  • Filename
    139990