A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method

Author

Matsukawa, Kazuo ; Obata, Koji ; Mitani, Yosuke ; Dosho, Shiro

Author_Institution

Panasonic Corp., Moriguchi, Japan

fYear

2012

fDate

13-15 June 2012

Firstpage

160

Lastpage

161

Abstract

This paper proposes a new power and area efficient circuit configurations, and also an optimization design method for such configurations. Two types of loopfilters are fabricated, one is a third-order integrator with single opamp for mobile TV-tuners (Modulator A) and the other is a fourth-order (Modulator B) for wide-band mobile receivers. Modulator A and Modulator B are fabricated in 65 nm and 40 nm CMOS processes, respectively. Results show that the new filter with an efficient optimization tool is a very powerful way to develop high efficient ΔΣ.

Keywords

CMOS integrated circuits; circuit optimisation; delta-sigma modulation; operational amplifiers; CMOS process; area efficient circuit configuration; bandwidth 10 MHz; continuous time ΔΣ modulator; high-order single opamp integrator; loopfilter; mobile TV tuner; optimization-based design method; power efficient circuit configuration; single opamp; size 65 nm to 40 nm; third-order integrator; wide-band mobile receiver; Calibration; Filtering theory; Harmonic distortion; Modulation; Optimization; Power harmonic filters; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2012 Symposium on

Conference_Location

Honolulu, HI

Print_ISBN

978-1-4673-0848-9

Electronic_ISBN

978-1-4673-0845-8

Type

conf

DOI

10.1109/VLSIC.2012.6243839

Filename

6243839