DocumentCode
2662670
Title
Table of contents
fYear
2012
fDate
7-9 May 2012
Abstract
The following topics are dealt with: optimization; asynchronous digital circuits; asynchronous fully digital delay locked loop; DDR SDRAM data; CAD; arithmetic circuits; clock scheduling; fault tolerance; and self synchronous circuits.
Keywords
CAD; SRAM chips; asynchronous circuits; circuit optimisation; clocks; delay lock loops; fault tolerance; CAD; DDR SDRAM data; arithmetic circuit; asynchronous digital circuit; asynchronous fully digital delay locked loop; clock scheduling; fault tolerance; optimization; self-synchronous circuit;
fLanguage
English
Publisher
ieee
Conference_Titel
Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on
Conference_Location
Lyngby
ISSN
1522-8681
Print_ISBN
978-1-4673-1360-5
Type
conf
DOI
10.1109/ASYNC.2012.10
Filename
6243874
Link To Document