Systematic VHDL code generation using pipeline operations produced by high level synthesis

Author

Arató, Péter ; Kandár, Tibor

Author_Institution

Dept. of Control Eng. & Inf. Technol., Budapest Univ. of Tech. & Econ., Hungary

fYear

2003

fDate

4-6 Sept. 2003

Firstpage

191

Lastpage

196

Abstract

We present a method for systematic VHDL code generation from a data-flow representation. In such cases, a methodology is needed that yields a hardware description, which are synthetized and mapped into an FPGA. This procedure speeds up the development of the prototype, reduces the time-to-market, and helps the logic and timing simulation.

Keywords

data flow graphs; field programmable gate arrays; hardware description languages; high level synthesis; pipeline processing; program compilers; FPGA; data-flow representation; field programmable gate arrays; high level synthesis; logic simulation; pipeline operation; system-level synthesis; systematic VHDL code generation; Automatic control; Control engineering; Hardware; High level synthesis; Information technology; Logic; Multiplexing; Pipelines; Research and development; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Signal Processing, 2003 IEEE International Symposium on

Print_ISBN

0-7803-7864-4

Type

conf

DOI

10.1109/ISP.2003.1275837

Filename

1275837

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2663657