A Reliability-Aware Partitioner for Multi-FPGA Platforms

This paper presents a partitioning approach for reliable systems on multi-FPGA platforms. We propose a Mixed Integer Linear Programming model that distributes a system composed of self-checking and independently recoverable areas among the available devices, by achieving a uniform distribution and minimizing inter-FPGA communication. The partitioner takes into account also possible recovery actions needed during the system´s lifetime, by reserving a suitable spare area for relocations in case of faults physically damaging the device. With respect to literature, where the partitioning problem is solved by heuristic algorithms based on non-accurate models, we propose a partitioner that identifies the global optimal solution in an acceptable execution time and can be integrated in an overall reliability-aware design flow.