Process-variation tolerant design techniques for multiphase clock generation

Author

Nagaraju, Manohar ; Wei Wu ; Charles, Cameron T.

Author_Institution

Univ. of Utah, Salt Lake City, UT, USA

fYear

2010

fDate

12-15 Dec. 2010

Firstpage

102

Lastpage

105

Abstract

This paper presents the design of a process-variation tolerant Delay-Locked Loop (DLL) for use in multiphase clock generation. A transistor sizing methodology to reduce delay variations with threshold voltage (V_t) mismatch in the Voltage Controlled Delay Line (VCDL) is proposed. Additionally, a new digital calibration scheme is proposed to further reduce the delay variations. A DLL was fabricated in a 0.6μm CMOS process and measurement results indicate reduction in the maximum mismatch in the timing error among the delay blocks from 40.1ps (3.28°) to 13.44ps (1.09°).

Keywords

CMOS analogue integrated circuits; clock and data recovery circuits; clocks; delay lines; delay lock loops; integrated circuit design; voltage control; CMOS process; DLL; VCDL; delay variations; delay-locked loop; digital calibration scheme; multiphase clock generation; process-variation tolerant design techniques; size 0.6 mum; threshold voltage mismatch; time 40.1 ps to 13.44 ps; transistor sizing methodology; voltage controlled delay line; Clock and Data Recovery; Delay-Locked Loop; Multiphase clock generation; Process variation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on

Conference_Location

Athens

Print_ISBN

978-1-4244-8155-2

Type

conf

DOI

10.1109/ICECS.2010.5724464

Filename

5724464