Noise optimization of BiCMOS operational amplifiers

Author

Aho, Jarmo ; Halonen, Kari

Author_Institution

Dept. of Electr. Eng., Helsinki Univ. of Technol., Espoo, Finland

fYear

1990

fDate

1-3 May 1990

Firstpage

3201

Abstract

To improve the offset and noise performances of CMOS amplifiers, several BiCMOS operational amplifiers with bipolar junction transistors (BJTs) applied in the input stage are presented. The speed performance of the amplifiers is improved. The input stage bias current is optimized for minimum noise as a function of the source resistance. Measurements on the realized BiCMOS amplifiers confirm the theory. In integrated circuits the theory allows the amplifier noise performance to be optimized because both the source resistance and the bias current of the amplifiers can be designed

Keywords

BIMOS integrated circuits; electron device noise; linear integrated circuits; operational amplifiers; BiCMOS amplifiers; amplifier noise performance; input stage bias current; integrated circuits; minimum noise; monolithic IC; noise optimisation; op amp; operational amplifiers; source resistance; speed performance; BiCMOS integrated circuits; Bipolar transistors; Circuit noise; Density measurement; Electronic circuits; Integrated circuit noise; Noise measurement; Operational amplifiers; Performance evaluation; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., IEEE International Symposium on

Conference_Location

New Orleans, LA

Type

conf

DOI

10.1109/ISCAS.1990.112693

Filename

112693