A single-chip pipelined 2-D FIR filter using residue arithmetic

Author

Shanbhag, Naresh R. ; Siferd, Raymond E.

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

fYear

1990

fDate

21-25 May 1990

Firstpage

98

Abstract

The authors present novel circuits for residue arithmetic, which have been configured to form a 3×3 finite impulse response (FIR) filter with programmable coefficients. The filter has a pipelined architecture and includes testability in the form of scan path. Area efficient circuits for residue adders, subtractors, and binary-to-residue converters have been designed. An encoding scheme has been used to reduce the residue multiplier area. A tree architecture for residue-to-binary conversion has been developed. The filter is timed with a two-phase clock, which has an estimated frequency of 15 MHz

Keywords

digital arithmetic; digital filters; digital signal processing chips; pipeline processing; 15 MHz; 2D filter; binary-to-residue converters; encoding; finite impulse response filter; pipelined architecture; programmable coefficients; residue adders; residue arithmetic; residue-to-binary conversion; scan path; single-chip pipelined 2-D FIR filter; subtractors; testability; tree architecture; two-phase clock; Adders; Arithmetic; Circuit testing; Concurrent computing; Digital signal processing chips; Encoding; Filtering; Finite impulse response filter; Frequency estimation; Image converters;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference, 1990. NAECON 1990., Proceedings of the IEEE 1990 National

Conference_Location

Dayton, OH

Type

conf

DOI

10.1109/NAECON.1990.112748

Filename

112748