VMOS, UMOS technology simulation

Author

Kersys, T. ; Andriukaitis, D. ; Anilionis, R.

Author_Institution

Dept. of Electron. Eng., Kaunas Univ. of Technol.

fYear

0

fDate

0-0 0

Firstpage

537

Lastpage

542

Abstract

VMOS, UMOS ("V"-groove-metal-oxide-silicon) transistors drain and gate are formed in the groove of "V" or "U" form. Expanding channel area, therefore VMOS and UMOS structures may use in the power chips. Using VMOS, UMOS is saving 40% free space than using NMOS technology. Nanostructures dimensions are very small, so it is important to keep pn junction in a right depth, in the all semiconductor manufacturing technological process. Analyzing influence to forming structure of each technological operation is used mathematical simulation program SUPREM IV. VMOS and UMOS technological operation was simulated in micro and nano level

Keywords

MOSFET; nanotechnology; semiconductor device manufacture; semiconductor process modelling; U-groove-metal-oxide-silicon; V-groove-metal-oxide-silicon; mathematical simulation program; nanostructure dimension; nanotechnology; pn junction; power chip; semiconductor manufacturing technological process; transistor; Analytical models; Boron; Doping; Ion implantation; Manufacturing processes; Semiconductor process modeling; Silicon; Space technology; Substrates; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Technology Interfaces, 2006. 28th International Conference on

Conference_Location

Cavtat/Dubrovnik

ISSN

1330-1012

Print_ISBN

953-7138-05-4

Type

conf

DOI

10.1109/ITI.2006.1708538

Filename

1708538