Real-time canny edge detection parallel implementation for FPGAs

Edge detection is one of the most fundamental algorithms in digital image processing. The Canny edge detector is the most implemented edge detection algorithm because of its ability to detect edges even in images that are intensely contaminated by noise. However, this is a time consuming algorithm and therefore its implementations are difficult to reach real time response speeds. Especially nowadays where the demand for high resolution image processing is constantly increasing, the need for fast and efficient edge detector implementations is ever so present. A new parallel Canny edge detector FPGA implementation is proposed in this paper to answer this demand. This design takes advantage of 4-pixel parallel computations to achieve high throughput without increasing the on-chip memory demands. Synthesis and simulation results are presented to prove the design´s efficiency and high frames per second rate.