A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding

This work proposes a new hardware architecture for the H.264/AVC CAVLC (Context-Based Adaptive Variable Length Coding) entropy encoder. The architecture is composed of a macro-pipeline formed by 3 stages: (i) Scan, (ii) Encoding and (iii) Assembler. Our architecture employs a new scheme to process two coefficients each cycle at the Scan stage. Thus, the fixed bottleneck at this stage is eliminated obtaining a significant performance gain compared to related works. In order to allow this increase in performance, the proposed architecture also processes in a two-way parallel hardware the most frequent syntactic elements (Level and Run_Before) of the algorithm. The synthesis for Xilinx Virtex-5 FPGAs demonstrates that the proposed architecture is able to reach the performance for real-time HDTV encoding while running at 60 MHz. At its maximum frequency, our design is able to achieve the encoding of 115 HD1080p fps (frames per second) in FPGA implementation.