Efficient WCDMA digital down converter design using system generator

In this paper, the design and implementation of the digital up converter (DUC) on Xilinx FPGA for WCDMA is presented. A powerful system level design tool, Xilinx system generator, is adopted to shorten the design cycle and increase the design productivity. The proposed DDC includes DDS, mixer and three cascaded stages of filters. Using Vitex-5 DSP48E slices, the maximum operation speed of the complex multiplier reaches 368.64 MHz. The DDS submodule is designed and produced by Xilinx DDS compiler. The remaining submodules of the DDC,such as the RRC filter and the half-band filters, are co-designed using MATLAB FDATool and Xilinx FIR compiler with considerations of tradeoff between receive path requirements of WCDMA, algorithm and hardware implementation complexity. We have successfully verified the system generator module of the DDC using the MATLAB module of it. Finally, the DDC is implemented on Xilinx XC5VSX50T FPGA device. And its performance and costs are also addressed.