DocumentCode
2668155
Title
Comparison of DEM and BEET linearization techniques for flash analog-to-digital converters using a SFDR metric
Author
McGuinness, Christopher D. ; Balster, Eric J. ; Scarpino, Frank A.
Author_Institution
Dept. of Electr. & Comput. Eng., Univ. of Dayton, Dayton, OH, USA
fYear
2010
fDate
12-15 Dec. 2010
Firstpage
871
Lastpage
877
Abstract
Data converter linearization has been a subject of some interest for most of the past decade. New methods of linearizing analog-to-digital converters (ADC) continue to be developed. Various linearization methods are available but their comparative strengths and weaknesses are not easily recognizable, making it somewhat difficult to determine which compensator would provide maximum benefit for a specific device. This paper provides a performance comparison of two promising real-time linearization methods for flash ADCs: the in-device DEM method, and the peripherally-implemented BEET method. SFDR is used as the primary performance metric. It is found that BEET is the superior compensator for devices with INL values larger than 0.25 LSB and DNL values larger than 0.25 LSB. DEM is the better-performing compensator for devices with INL/DNL values below the BEET-preferred region.
Keywords
analogue-digital conversion; integrated circuit design; linearisation techniques; ADC; BEET linearization technique; DEM linearization technique; SFDR metric; bit-extended error tables; compensator; data converter linearization; dynamic element matching; flash analog-to-digital converters; indevice DEM method; peripherally-implemented BEET method; Analog-digital conversion; error correction; linear approximation; nonlinear distortion; simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics, Circuits, and Systems (ICECS), 2010 17th IEEE International Conference on
Conference_Location
Athens
Print_ISBN
978-1-4244-8155-2
Type
conf
DOI
10.1109/ICECS.2010.5724651
Filename
5724651
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