SPICE modeling of 55 nm embedded SuperFlash® technology 2T memory cells

Author

Martinie, S. ; Rozeau, O. ; Tadayoni, M. ; Raynaud, C. ; Nowak, E. ; Hariharan, S. ; Do, N.

Author_Institution

CEA-LETI, Grenoble, France

fYear

2015

fDate

23-26 March 2015

Firstpage

24

Lastpage

28

Abstract

Embedded Flash NVM has become a key component in many applications, such as data processing, industrial electronics, automotive electronics, consumer electronics and wireless communications. SuperFlash^® technology is based on the split-gate concept, using source-side electron injection for programming. The aim of this work is to propose, for the first time, a SPICE macro-model of the 2T (Select Gate and Floating Gate) 3rd generation SuperFlash cell [Hidaka], implemented in a 55 nm CMOS technology. A parameter extraction procedure is also proposed, showing a good agreement between the model and measurements.

Keywords

CMOS memory circuits; SPICE; embedded systems; flash memories; 2T memory cells; 3rd generation SuperFlash cell; CMOS technology; Hidaka; SPICE macro-model; SPICE modeling; embedded SuperFlash technology; embedded flash NVM; floating gate; parameter extraction procedure; select gate; size 55 nm; source-side electron injection; split-gate concept; Current measurement; Transistors; Voltage measurement; World Wide Web;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2015 International Conference on

Conference_Location

Tempe, AZ

ISSN

1071-9032

Print_ISBN

978-1-4799-8302-5

Type

conf

DOI

10.1109/ICMTS.2015.7106102

Filename

7106102