A SystemC AMS model of an 12C bus controller

Author

Alassir, M. ; Denoulet, J. ; Romain, O. ; Garda, P.

Author_Institution

Lab. des Instrum. et Systemes d´´Ile-de-France, Univ. Pierre et Marie Curie, Paris

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

154

Lastpage

158

Abstract

The authors present the design of an intellectual property (IP) modeling the interface controller for an inter-integrated controller channel (I2C) bus. AMS IPs such as bus interfaces, whose behaviour follows the bus protocols in terms of packet structure, timing constraints or control modes can offer solutions for the issue of communications between a system on a chip and its external environment. The model of our controller is written in SystemC in association with a SystemC-AMS description of the analog block. Simulation results are presented

Keywords

industrial property; integrated circuit modelling; system buses; system-on-chip; I2C bus controller; SystemC AMS; bus interfaces; bus protocols; intellectual property; inter-integrated controller channel; packet structure; system-on-chip; timing constraints; Character generation; Clocks; Communication system control; Digital control; Intellectual property; Protocols; Signal design; System-on-a-chip; Telecommunication control; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708709

Filename

1708709