A test structure for reliability analysis of CMOS devices under DC and high frequency AC stress

Author

Matsuda, T. ; Ichihashi, K. ; Iwata, H. ; Ohzone, T.

Author_Institution

Dept. of Inf. Syst. Eng., Toyama Prefectural Univ., Toyama, Japan

fYear

2015

fDate

23-26 March 2015

Firstpage

86

Lastpage

89

Abstract

A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I - V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were analyzed. The dominant degradation origins in nMOS and pMOS devices can be attributed to HCI and NBTI, respectively.

Keywords

CMOS integrated circuits; MOSFET; hot carriers; integrated circuit reliability; integrated circuit testing; invertors; negative bias temperature instability; semiconductor device reliability; semiconductor device testing; CMOS inverters; DC stress; HCI; Kelvin connected selector switches; MOSFET; NBTI; alternative current mode; direct current mode; dominant degradation origins; high frequency AC stress; hot carrier injection; input pulse generation block; monitor inverter blocks; nMOS device; negative bias temperature instability; pMOS devices; reliability analysis; ring oscillator; test structure; Degradation; Logic gates; MOS devices; Reliability; Stress; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronic Test Structures (ICMTS), 2015 International Conference on

Conference_Location

Tempe, AZ

ISSN

1071-9032

Print_ISBN

978-1-4799-8302-5

Type

conf

DOI

10.1109/ICMTS.2015.7106114

Filename

7106114