Behavioral synthesis technique for flexible IP´s communications

Author

Kamel, Smiri ; Bennour, Imed ; Baganne, Adel ; Tourki, Rached ; Jemai, Abderrazek

Author_Institution

Fac. of Sci., E..E., Monastir

fYear

2006

fDate

5-7 Sept. 2006

Firstpage

390

Lastpage

393

Abstract

Among factors limiting the reuse of intellectual property (IPs) blocks into wide range of systems on chips (SoCs) is the inflexibility of their communication protocols. This paper presents an approach for designing IP blocks with relaxed timing constraints to exchange data with various environments. The approach is based on decoupling computation from communication and on an adequate scheduling of operations during the high level synthesis of computation units. Experimentations performed on the MPEG4 intraprediction IP block show the efficiency of our solution

Keywords

high level synthesis; industrial property; integrated circuit design; logic design; protocols; scheduling; system-on-chip; IP communications; IP reuse; MPEG4 intraprediction IP block; SoC; behavioral synthesis technique; communication protocols; decoupling computation; high level synthesis; intellectual property blocks; scheduling; systems on chips; Costs; High level synthesis; Intellectual property; MPEG 4 Standard; Network-on-a-chip; Processor scheduling; Protocols; Standards development; System-on-a-chip; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006. International Conference on

Conference_Location

Tunis

Print_ISBN

0-7803-9726-6

Type

conf

DOI

10.1109/DTIS.2006.1708719

Filename

1708719