A new parallel algorithm for full-digital phase-locked loop for high-throughput carrier and timing recovery systems

A parallel algorithm for a full-digital phase-locked loop for high-throughput adaptive carrier and timing recovery systems has been developed. The proposed algorithm separately estimates an initial phase and a period fluctuation for a sampled signal, whereas they are simultaneously estimated by conventional algorithms. The new algorithm increases the pull-in frequency range by 1.6 times and reduces the convergence time by 41 %, compared to those of conventional parallel algorithms. Hardware for a carrier and timing recovery system utilizing interpolation with the maximum bit rate of 6.9 Gb/s was designed using 40 nm CMOS technology, resulting in a practical cell area of 0.081 μm² for a 60 GHz millimeter-wave-based wireless communication application.