VLSI implementation of reconfigurable cells for RFU in embedded processors

The execution of operations on data shorter than the native wordlenght usually decreases the performance of standard microprocessors. In order to overcome this issue, various methods, based on reconfigurable structures, have been presented in literature. These structures are normally realized as an array of elementary reconfigurable cells. A common solution for the realization of elementary reconfigurable cells is that based on Look-Up Tables. In [4], we presented a new reconfigurable cell based on a full adder; the final aim was to obtain a new structure that, paying the price of slightly reduced flexibility, requires less silicon area and power, being ever faster than the “traditional” solution. In this paper, we present an exhaustive evaluation of the proposed cell. Our analysis is based on simulations, for the estimation of delay and power consumption, and on layout design, to evaluate area occupancy.