High-level address exploration for an error correction optical disk subsystem: improving design productivity

In most real-time multimedia systems, major design bottlenecks are related to memory organisation and management related issues. Usually, in order to meet design constraints at low cost, designers of the memory management units directly think about low-level (register-transfer level) implementation aspects of the architecture. However, this approach typically results into time-consuming global design iterations. In contrast, we propose a high-level design exploration methodology where design bottlenecks related especially to the address generation issues are exposed as early as possible in the design trajectory, hence reducing design time considerably. The effectiveness of our approach is illustrated on the memory processor of an optical disk error correction application, Using our approach, a substantial part of the design search space has been explored in a few man-weeks instead of the months of effort required by more conventional design flows. Furthermore, not only design time is dramatically improved but also implementation cost and system performance, hence resulting in a highly productive design flow