DocumentCode
2671618
Title
FASSAD: Fault simulation with sensitivities and depth-first propagation
Author
Sureshkumar, P.R. ; Jacob, James ; Srinivas, M.K. ; Agrawal, Vishwani D.
Author_Institution
Hindustan Aeronautics Ltd., Bangalore, India
fYear
1993
fDate
16-18 Nov 1993
Firstpage
66
Lastpage
71
Abstract
We use depth-first propagation of fault effects to quickly terminate the simulation of detected faults. Using the true logic states of signals, gates are classified as either definitely sensitive or potentially sensitive. Based upon this classification, we formulate rules for efficient propagation of faulty circuit events. These techniques are implemented in a single fault propagation (SFP) program. Results on benchmark circuits demonstrate that the depth-first propagation requires smaller number of gate evaluations compared to the conventional breadth-first propagation. Our technique takes smaller CPU time compared to a concurrent fault simulator for the ISCAS85 benchmarks and a differential parallel fault simulator for some of the ISCAS89 sequential benchmarks
Keywords
computational complexity; digital simulation; fault diagnosis; logic testing; sequential circuits; CPU time; FASSAD; ISCAS85 benchmarks; ISCAS89 sequential benchmarks; benchmark circuits; concurrent fault simulator; depth-first propagation; differential parallel fault simulator; true logic states; Benchmark testing; Circuit faults; Circuit simulation; Circuit testing; Electrical fault detection; Jacobian matrices; Logic circuits; Logic gates; Sequential analysis; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Symposium, 1993., Proceedings of the Second Asian
Conference_Location
Beijing
Print_ISBN
0-8186-3930-X
Type
conf
DOI
10.1109/ATS.1993.398781
Filename
398781
Link To Document