DocumentCode
2671789
Title
Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices
Author
Gundersen, Henning ; Berg, Yngvar
Author_Institution
Microelectron. Syst. Group, Univ. of Oslo, Oslo
fYear
2007
fDate
13-16 May 2007
Firstpage
30
Lastpage
30
Abstract
This paper presents ternary counters using balanced ternary notation. The balanced ternary counters can replace binary full adders or counters in fast adder structures. The circuits use recharged CMOS semi-floating gate (RSFG) devices. By using balanced ternary notation, it is possible to build balanced ternary addition circuits, which can add both negative and positive operands, by using the same adder blocks. The circuit operates at a clock frequency of 1 Ghz. The supply voltage 1.0 Volt.
Keywords
CMOS logic circuits; adders; logic design; ternary logic; balanced ternary counter; frequency 1 GHz; recharged CMOS semifloating gate device; ternary addition circuit; voltage 1.0 V; Adders; CMOS technology; Clocks; Counting circuits; Digital arithmetic; Frequency; Informatics; Microelectronics; Multivalued logic; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on
Conference_Location
Oslo
ISSN
0195-623X
Print_ISBN
0-7695-2831-7
Type
conf
DOI
10.1109/ISMVL.2007.23
Filename
4215953
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