A Ternary Analog-to-Digital Converter System

An analog-to-digital converter (ADC) system, consisting of a combination of a pipelined ADC and a finite-duration impulse response (FIR) filter, has been proposed. In conventional 1.5-bit/stage pipelined ADC´s, ternary-valued signals are used internally for correcting conversion errors. The signals are then converted into the ADC binary output, which is supplied to a digital filter for additional signal processing in the binary domain. In the present approach, in contrast, the internal ternary-valued signals are interpreted as the signed-digit number of {-1, 0,1}, and directly forwarded to an FIR filter that employs the SD addition algorithm. A combination of an 8-bit 1.5-bit/stage pipelined ADC and a third-order cascaded-integrator comb (CIC) filter is considered as an example to estimate the performance. Our simulation indicates that the digital processing time can be reduced by more than a factor of two in the present approach.