Experiment Result of Down Literal Circuit and Analog Inverter on CMOS Double-Polysilicon Process

Author

Inaba, Motoi

Author_Institution

Dept. of Ind. Inf., Tsukuba Univ. of Technol., Tsukuba

fYear

2007

fDate

13-16 May 2007

Firstpage

58

Lastpage

58

Abstract

In this paper, the transistor-level layouts and the experiment results of the down literal circuit (DLC) and the analog inverter (AINV) on a CMOS double- poly silicon process are presented. DLC and AINV are the voltage-mode circuits to realize the down literal function with a variable threshold and the inverse function, respectively. Through the experiment of test- production LSI chips, the good transfer characteristics of DLC and AINV are confirmed. For instance, the threshold voltage of DLC is in error by less than 0.03[V] only. AINV achieves the high linearity within 86% of all signal range and the errors of the output voltage are within +0.01 [V] and -0.11 [V]. The results fully satisfy the requirements for the 5-volt 6-value logic circuits or more. And, the voltage comparator is taken up as an application of DLC and AINV.

Keywords

CMOS analogue integrated circuits; comparators (circuits); invertors; large scale integration; 5-volt 6-value logic circuit; CMOS double-polysilicon process; analog inverter; down literal circuit; test-production LSI chip; threshold voltage; voltage comparator; voltage-mode circuit; CMOS analog integrated circuits; CMOS process; Circuit testing; Inverters; Large scale integration; Linearity; Logic circuits; Production; Silicon; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 2007. ISMVL 2007. 37th International Symposium on

Conference_Location

Oslo

ISSN

0195-623X

Print_ISBN

0-7695-2831-7

Type

conf

DOI

10.1109/ISMVL.2007.20

Filename

4215981