• DocumentCode
    2673165
  • Title

    Power distribution strategies based on current estimation and simulation of lossy transmission lines in conjunction with power isolation circuits

  • Author

    Jagau, U. ; Dyck, K.P. ; Grabinski, H. ; Iden, H.-J. ; Kuboschek, M.

  • Author_Institution
    Hannover Univ., West Germany
  • fYear
    1990
  • fDate
    23-25 Jan 1990
  • Firstpage
    288
  • Lastpage
    297
  • Abstract
    Investigations have shown that the layout of power lines and isolation circuits as well as the modules´ circuit switching has a large influence on the behavior of the whole system. A current estimation strategy for the calculation of the module current consumption in CMOS technology is investigated. The electrical behavior of losses in signal and power lines is taken into account. An efficient current estimation is introduced with a new program-SIMCURRENT. Another program carries out analog circuit simulations including the modelling of coupled lossy transmission lines. Fast and accurate estimates of the Idd-current are carried out by SIMCURRENT. Simulations-often not possible with classical circuit analysis programs-were made with the program LISM. Regarding monolithic systems, one must include power isolation circuits in the power rail system. A proper layout of the global supply network (not using the lowest resistive layout) is proposed
  • Keywords
    CMOS integrated circuits; VLSI; circuit layout CAD; integrated circuit technology; CMOS technology; LISM; SIMCURRENT; analog circuit simulations; coupled lossy transmission lines; current estimation strategy; electrical behavior of losses; global supply network; layout of power lines; module current consumption; power isolation circuits; power lines; power rail system; proper layout; Analog circuits; CMOS technology; Circuit simulation; Coupling circuits; Isolation technology; Power distribution; Power system modeling; Propagation losses; Semiconductor device modeling; Switching circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-8186-9013-5
  • Type

    conf

  • DOI
    10.1109/ICWSI.1990.63912
  • Filename
    63912