Timing yield analysis of pipelined circuits under device variability

Due to continuous quest for greater throughput, pipelined circuits are used to support multi-cycle processing at greater clock frequencies, leaving limited design margins. Under statistical device variations, the delay distributions of the pipeline stages follow a skewed distribution in highly scaled devices. Therefore, in order to determine the maximum operating frequency of the pipelined circuits, accurate estimation of the slowest pipeline stage will have to be determined. This study shows that identifying the slowest pipeline stage using Clark´s approximation will produce quite optimistic results and will lead to significant yield loss. Moreover, it has been shown that while estimating the yield, the stage delay distributions in both low-to-high and high-to-low transitions need to be considered and hold time distributions should also be considered along with setup time distributions.