• DocumentCode
    2674505
  • Title

    Hardware implementation of a wavelet based image compression coder

  • Author

    Singh, J. ; Antoniou, A. ; Shpak, D.J.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Victoria Univ., BC, Canada
  • fYear
    1998
  • fDate
    5-6 Jun 1998
  • Firstpage
    169
  • Lastpage
    173
  • Abstract
    A VLSI architecture designed to perform real-time image compression using wavelets is described. The two basic modules of the architecture are a 2-D wavelet transform generator and a coder based on the SPIHT algorithm for lossy image compression. A folded architecture is proposed for computing the 2-D wavelet transform. The architecture uses 3 parallel computational units and 2 storage units. The hardware for the SPIHT coder uses 2 content addressable memories and 3 random access memories. The designs are modular and can easily be extended for different levels of wavelet decomposition and filter lengths. The derived architecture has been functionally verified for an 8×8 image size by simulating its VHDL code using Mentor Graphics
  • Keywords
    VLSI; band-pass filters; content-addressable storage; data compression; digital filters; digital signal processing chips; image coding; modules; parallel architectures; random-access storage; transform coding; wavelet transforms; 2D wavelet transform generator; Mentor Graphics; RAM; SPIHT algorithm; SPIHT coder; VHDL code simulation; VLSI architecture; content addressable memories; filter bank; filter lengths; folded architecture; hardware implementation; image size; lossy image compression; modular design; parallel computational units; random access memories; real-time image compression; storage units; wavelet based image compression coder; wavelet decomposition; Associative memory; Computer architecture; Concurrent computing; Filters; Graphics; Hardware; Image coding; Random access memory; Very large scale integration; Wavelet transforms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advances in Digital Filtering and Signal Processing, 1998 IEEE Symposium on
  • Conference_Location
    Victoria, BC
  • Print_ISBN
    0-7803-4957-1
  • Type

    conf

  • DOI
    10.1109/ADFSP.1998.685718
  • Filename
    685718