DocumentCode
2674794
Title
VLSI yield optimization based on the sub-processing-element level redundancy
Author
Zhao, Tianxu ; Hao, Yue ; Jiao, Yongchang
Author_Institution
Inst. of Microelectron., Xidian Univ., Xi´´an, China
fYear
2000
fDate
2000
Firstpage
41
Lastpage
46
Abstract
An optimal allocation model of the sub-processing-element (sub-PE) level redundancy is developed by using a genetic algorithm. The average defect density D and the support circuit parameter δ are considered in this allocation model to accurately analyze the element yield. Under the condition of the given area constraint, simulation results indicate that the number of the optimal redundant sub-circuits added to a PE and the PE´s yield are decrease for any given average defect density D as δ increase. Further, the number of the optimal redundant sub-circuits is increase, while the optimal yield of the PE is decrease for any given support circuit area parameter δ as D increases
Keywords
VLSI; circuit optimisation; genetic algorithms; integrated circuit modelling; integrated circuit reliability; integrated circuit yield; redundancy; VLSI yield optimization; area constraint; average defect density; genetic algorithm; optimal allocation model; optimisation model; sub-processing-element level redundancy; Adders; Circuit simulation; Constraint optimization; Electronic mail; Genetic algorithms; Integrated circuit yield; Microelectronics; Redundancy; Registers; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Defect and Fault Tolerance in VLSI Systems, 2000. Proceedings. IEEE International Symposium on
Conference_Location
Yamanashi
ISSN
1550-5774
Print_ISBN
0-7695-0719-0
Type
conf
DOI
10.1109/DFTVS.2000.886972
Filename
886972
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